Muhammad Mujeeb Awan

About

Electrical engineer with 3+ years of industry experience in embedded systems and FPGA design, currently pursuing MS at NUST with research in silicon nitride photonics. My thesis focuses on designing a high-efficiency apodized focusing grating coupler, achieving 69.1% coupling efficiency — currently being fabricated at LAAS-CNRS, France. I combine strong hardware engineering fundamentals with hands-on simulation, edge AI deployment, and photonic device design.

Research

High-Efficiency Apodized Focusing Grating Coupler on Silicon Nitride

MS Thesis · NUST · Supervisor: Dr. Usman Zabit · Oct 2024 – Present

Designed an apodized focusing grating coupler (FGC) on a 300 nm silicon nitride platform for fiber-to-chip coupling at 1550 nm. The device uses a single full-etch process with SiO₂/PMMA cladding, achieving 69.1% coupling efficiency (−1.61 dB) to SMF-28 fiber — a 43% improvement over the uniform baseline (48%).

The apodization ramps the duty cycle from 12.5% to 25% across 260 grating teeth (21 sections) to shape the radiated field for optimal Gaussian mode matching. A parametric sweep of 1,472 FEXEN electromagnetic simulations was conducted to construct the effective index lookup table. The complete design-to-GDS pipeline was developed in MATLAB (3,000+ lines). The device is currently being fabricated at LAAS-CNRS, Toulouse, France.

Silicon Nitride Grating Coupler FEXEN MATLAB Phase Matching Apodization GDS Layout KLayout Angular Spectrum

E-field propagation from grating surface showing beam focusing at fiber height

Coupling efficiency breakdown: simulated beam vs SMF-28 fiber mode

Fabrication-ready GDS layout with 260 curved teeth

Beam focusing and coupling efficiency vs fiber height for best design (Sim #34)

International Collaboration

LAAS-CNRS, Toulouse, France — Device fabrication.
University of Málaga, Spain — Collaboration on focusing grating coupler layout methodology (Robert Halir).

Projects

Security Dashboard with live stream, real-time alerts, and 24h statistics

Face Recognition Security System

NVIDIA Jetson AGX Orin 64GB · 2025 · Best Project Award, NUST

Production-ready real-time face detection and recognition system deployed on NVIDIA Jetson AGX Orin. GPU-accelerated SCRFD detection with TensorRT FP16 optimization (25-30 FPS), FAISS GPU for sub-millisecond similarity search across 1000+ faces. Features multi-face tracking, RTSP camera integration (Hikvision), FastAPI backend with WebSocket real-time alerts, and a complete web dashboard with JWT authentication.

TensorRT FAISS FastAPI Python CUDA SCRFD WebSocket RTSP Jetson AGX Orin

Admin panel with person enrollment and watchlist management

Alert management page with filtering, threat levels, and guard verification

NUST Chatbot main interface with system monitor showing CPU inference

Chatbot answering eligibility criteria with source documents

NUST Admissions Chatbot — Offline RAG GitHub → Demo Video →

CPU-Only Deployment · 2026 · NUST Local Chatbot Competition

An offline retrieval-augmented generation (RAG) chatbot for NUST admissions guidance. Runs entirely on consumer hardware — no GPU, no cloud, no internet after initial setup. Processes 74 Q&A pairs and 12 official PDFs (1,070 indexed documents) through a FAISS vector store, retrieves the top-5 relevant chunks, and generates grounded answers using a quantized Qwen2.5-3B model (4-bit, ~2 GB) via CPU inference.

The system explicitly states knowledge gaps rather than hallucinating, displays source documents for transparency, and runs on just 4–6 GB RAM. Built with LangChain for pipeline orchestration, llama-cpp-python for inference, and Gradio for the web interface.

Python LangChain FAISS Qwen2.5-3B GGUF Quantization llama-cpp Gradio RAG Offline AI

Chatbot honestly saying I don't know instead of hallucinating

Experience

Embedded Systems Engineer

National Radio Telecommunication Corporation (NRTC), Islamabad · Apr 2022 – Present

FPGA digital design (Verilog, Xilinx Vivado), embedded software (C/C++, FreeRTOS on ESP32/STM32), GPU-accelerated AI deployment on NVIDIA Jetson platforms, PCB design, and communication protocol implementation (UART, SPI, I2C, CAN, Ethernet).

Lab Engineer

Air University, Islamabad · Sep 2021 – Apr 2022

Conducted lab sessions for undergraduate EE courses in embedded systems, digital design, and microcontroller programming.

Internee Engineer

National Electronic Complex of Pakistan (NECOP), Islamabad · Jul – Sep 2021

Designed energy-efficient arithmetic units for FPGA-based hardware accelerators using Verilog.

Education

MS Electrical Engineering

National University of Sciences and Technology (NUST), Islamabad · Sep 2024 – Present

Thesis: High-Efficiency Apodized Focusing Grating Coupler on Silicon Nitride Platform
Supervisor: Dr. Usman Zabit

BS Electrical Engineering

COMSATS University Islamabad (CUI), Wah Campus · Sep 2017 – Jul 2021

FYP: Automobile Black Box (IoT-based vehicle tracking and data logging system)

Skills

Photonics & Simulation

FEXEN EM Solver Angular Spectrum Phase Matching KLayout (GDS) MATLAB

Programming

C/C++ Python MATLAB Verilog Assembly

Embedded & FPGA

ESP32 STM32 Xilinx Vivado FreeRTOS PCB Design UART/SPI/I2C/CAN

AI & Computer Vision

TensorRT YOLOv8 FAISS OpenCV PyTorch NVIDIA Jetson

Tools

Git/GitHub FastAPI LaTeX Docker Linux